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1 features ? davic/dvb ? /ets300.429/itu-t j.83 annex a, c fully compliant direct if sampling (no second if down conversion required) or baseband input internal dc offset compensation 1024, 512, 256, 128, 64, 32, 16 qam and qpsk demodulation roll-off factor adapted to raised-cosine filtered signal (0.11 to 0.4) fully digital timing recovery variable symbol rate recovery anti-aliasing continuously variable digital filtering with symbol rate adaptive bandwidth (1 to 18.75m baud at the same sampling frequency) fully digital carrier recovery (coherent or differential for qpsk) robust equalizer acquisition selectable transversal or decision feedback equalizer dual phase/frequency offset recovery up to 12% of the symbol rate with no degradation mpeg2 frame synchronization reed-solomon decoder (204, 188, 8) de-interleaving (i = 12 and i = 17) energy dispersal descrambling i 2 c interface switch for separate bi-directional i 2 c bus-to-tuner to avoid phase noise problems due to i 2 integrated clock reference for tuner, especially designed for niu in can two agcs: analog and digital gains three program identifier (pid) filtering irq interrupt request generation to simplify monitoring bit error rate and packet error rate monitoring signal-to-noise ratio estimation, residual phase noise estimation automatic spectrum inversion jtag support 0.35 micron cmos technology, 3.3v operation 100-lead tqfp package description the AT76C651 is a dvb-compliant quadrature amplitude modulation (qam) demod- ulation circuit, which can be used in dvb and other applications using quadrature phase shift keying (qpsk) or qam transmission systems. the signal, after output from tuner and adjacent channels rejection filter, is externally sampled at if frequency. the signal is converted to digital format by an analog-to-digital converter and goes through several processing steps required for demodulation: automatic gain control, baseband down conversion, timing recovery with anti-aliasing filtering, square root raised-cosine receive filtering, carrier recovery and digital gain control and equaliza- tion (linear and decision feedback dual structure). the output from demodulation then goes through forward error decoding: dvb/davic de-mapping, frame synchroniza- tion, de-interleaving, reed-solomon decoding and spectrum de-randomization. the output before decoding may also be output directly for use with post-processing devices in applications other than dvb. an additional block situated in the back-end may be used to filter out programmable pids, which provides additional flexibility in interactive solutions or dvb data-broad- cast pc receive cards. it is especially designed for modem implementations with a 24- bit mask on one pid (medium access control) and can be used for return channel implementation. digital reception/ transmission ic integrated dvb? compliant qam demodulator AT76C651 rev. 1293c ? 06/00
AT76C651 2 figure 1. symbol of the AT76C651 qam demodulator ifqbb3 ifqbb2 ifqbb1 ifqbb0 qbb1 qbb0 ifibb5 ifibb3 ifibb2 ifibb1 ifibb0 ifibb4 tdo ti2cscl ti2csda tunclk dataout0 dataout1 dataout2 dataout4 dataout5 dataout6 dataout3 dataout7 irq frmvalid frmstart datavalid i 2 c a d d r 1 i2caddr0 oscmode lftpll i2cscl i2csda trst tms tck xtal_o xtal_i smplphase reset* adclk testadc pllctrl2 pllctrl0 pllctrl1 testmode tdi jtag i 2 c external a/d converter(s) if (10 bits) i (6 bits) q (6 bits) quartz osc xoclk xo pll rc phasym ensym ref2clk qam demodulator /n flagpid0 flagpid1 lock1 corfail corbyte lock2 a g c rc signal amplification control c s t p w m rc constant voltage (i 2 c controlled) mpeg2-ts output or i/q constellation test interface signal in ref_clk configuration output data control indicators vdd
AT76C651 3 table 1. signal description signal name function number of i/os pull-up voltage direction i2caddr i 2 c circuit address selection 2 no v dd3 i i2csda sda line of i 2 c 1 r = 15 k ? v dd5 i/o i2cscl scl line of i 2 c1nov dd5 i ti2csda i 2 c bus data line sda to/from tuner through bi-directional switch 1 r = 15 k ? v dd5 i/o ti2cscl i 2 c bus clock scl to tuner through switch 1 no v dd5 o ifibb if 6 msbs or i-baseband digital input 6 no v dd3 i ifqbb if 4 lsbs or q-baseband digital input 4 msbs 4 no v dd3 i qbb q-baseband digital input (2 lsbs) 2 no v dd3 i pllctrl pll division/bypass control 3 no v dd3 i xoclk crystal oscillator input 1 no v dd3 i xtal_i crystal input 1 no v dd3 i xtal_o crystal output 1 no v dd3 o oscmode oscillator input mode (0 for crystal, 1 for xo) 1 no v dd3 i lftpll low pass filter input to pll 1 no v dd3 a testadc a/d test pin (must be connected to vdd3 in standard operation) 1 no v dd3 i adclk sampling clock for external a/d converter 1 no v dd3 o smplphase external a/d sampling phase 1 no v dd3 i tdi jtag 1 no v dd3 i tdo jtag 1 no v dd3 o tms jtag 1 no v dd3 i tck jtag 1 no v dd3 i trst jtag 1 no v dd3 i dataout mpeg2-ts parallel byte <0:7> or serial bit stream output <0> 8 no v dd3 o corfail rs packets not corrected 1 no v dd3 o corbyte corrected byte indicator 1 no v dd3 o datavalid mpeg2-ts byte or bit output enable active at level 0 or on both edges 1nov dd3 o frmstart start of mpeg2-ts frame 1 no v dd3 o frmvalid valid mpeg2-ts frame control in parallel mode output 1 no v dd3 o flagpid pid filtering indicator 2 no v dd3 o irq interrupt request 1 no v dd3 o lock1 maskable lock signal 1 1 no v dd3 o lock2 maskable lock signal 2 1 no v dd3 o cstpwm configurable value output with pwm 1 no v dd5 o agc analog automatic gain control pwm 1 no v dd5 o tunclk 4 mhz reference oscillator output to tuner 1 no v dd5 o ref2clk half digital clock 1 no v dd3 o phasym test output signal 1 no v dd3 o ensym test output signal 1 no v dd3 o
AT76C651 4 figure 2. block diagram of the AT76C651 gnd ground gnd i2cgnd i 2 c ground gnd vdd +3.3v supply v dd3 pwr i2cvdd i 2 c power supply v dd5 pwr testmode test pin 1 no v dd3 i/o reset hard reset of circuit 1 no v dd3 i table 1. signal description (continued) signal name function number of i/os pull-up voltage direction dds baseband conversion timing recovery & continuous variable filtering sq. root nyquist agc2 digital equalizer le/dfe pwm agc1 analog de-interleaver (i=12/i=17) frame synchro symbol detection & dvb/davic de-mapping carrier recovery reed- solomon decoder (204, 188, 8) spectrum descrambler pid filtering mpeg-ts output parallel & serial (common interface) i 2 c interface digital in (if or bb)
AT76C651 5 functional description the following sections describe the main functions of all blocks included in the AT76C651 qam demodulation ic. interface to a/d converter (adc) a 10-bit external a/d converter must be connected to the AT76C651 in case of a signal in if frequency. the sam- pling clock of the adc must be taken on pin adclk of the chip. the digital outputs of the external adc must connect input ifibb5 to ifibb0 and input ifqbb3 to ifqbb0 (msb to lsb). the pin samplephase can be used to select the phase of the internal resampling clock, depending on the external adc propagation delay (see ? timing waveforms ? on page 35). in case of a signal in baseband, two external 6-bit adcs must be used. the sampling clock of the adcs must be taken on pin adclk of the chip. the digital outputs of the adcs must connect input ifibb5 to ifibb0 for i input and input ifqbb3 to ifqbb0 and qbb1 to qbb0 for q input (msb to lsb). samplephase should be connected as decribed in the previous paragraph. the sampling clock frequency (on adclk) is equal to the input frequency if the pll is used (either with a crystal or a crystal oscillator xo) or half the crystal frequency if the pll is bypassed (see ? oscillator and phase locked loop ? on page 7). two examples: if a 28 mhz crystal is used, the sampling frequency is 28 mhz; if a 60 mhz xo is used, the sampling frequency is 30 mhz. dc offset control an internal dc-offset compensation is done on the i and q baseband signals in order to compensate potential offsets created by a/d converters. direct digital synthesizer (dds) ? coarse tuning an if to baseband conversion from f o is then performed. the frequency f o is configurable, which reduces the con- straint on the relation between the saw filter center frequency and the chip oscillator. the frequency of the dds is further adjusted by the carrier frequency recovery in order to adjust exactly the received spectrum to the receive filter. ? analog ? automatic gain control (agc1) the signal level at the adc input is adjusted through a first agc loop. the power estimation block estimates the signal level at the output of the adc, compares it to a given level and generates a pulse width modulation (pwm) signal, which controls the analog gain. the pwm output generates a very stable control. since power estimation is done by digital loop control, only the output is given in pwm format for simpler implementation on board (only an rc filter with about 1khz cut-off bandwidth is required), whose fre- quency is f pwm = f ref /2. the power estimation is made over the entire signal sampled by the adc, thus including the adjacent channels and the target signal. this ensures that no analog saturation can happen due to the agc feedback. also, the power estimation of the analog gain control can be used in conjunction with the agc2 level (which indi- cates the power of the qam signal only) in order to compute the power of adjacent channels. this may be used to adjust the takeover point (top) of external amplifi- ers when several amplifiers are required on the board (typically in the tuner and after the saw filter). note that an i 2 c-controllable pwm is available for this purpose. digital timing recovery the baseband conversion output is then fed to the timing recovery block. this block integrates a digital timing loop, which estimates the best resampling time. this information is provided to a time-continuous filter, which interpolates the baseband signal and produces qam symbols at the recovered symbol rate. the interpolating filter ? s main property is its continuously autoadaptive bandwidth, which allows the demodulator to recover a wide range of symbol rate 1/t s , with the same perfomance, and avoids signal aliasing during resampling operation. square root raised-cosine nyquist receive filter (srrc) the srrc filter, with roll-off factor allowing demodulation of raised-cosine transmitted signals from 0.11 to 0.4, receives the signal from the timing recovery output and ensures an out-of-band rejection higher than 43 db. this significant rejection increases the back-off margin of the receiver against adjacent channels. digital automatic gain control (agc2) the internal digital agc performs a fine adjustment of the signal level at the equalizer input. this agc only takes into account the qam signal itself, since adjacent channels have been filtered out by the srrc, and thus compensates digitally the analog agc, which may have reduced the input power due to adjacent channels.
AT76C651 6 equalizer the equalizer is based on algorithms that provide blind and robust acquisition. the equalizer compensates for the dif- ferent impairments encountered on the network. two equalizer structures can be selected: transversal (powerful for long echoes) or decision feedback (powerful for strong short echoes). the equalizer central tap position is configurable. this allows an optimal compensation for post and pre-cursor echoes. the equalizer comprises 32 taps, which repre- sents a length of about 6.2 microseconds at 5m bauds. this allows a large compensation for echoes with signifi- cant delays, and a total compensation for significant (small attenuation) short echoes. carrier recovery ? fine tuning the carrier recovery block allows the acquisition and track- ing of a frequency offset as high as 12% of the symbol rate, even for low signal-to-noise ratios. the phase comparator algorithm provides a high-phase noise tolerance, which reduces the tuner cost. the frequency offset recovered by the chip can be monitored through the i 2 c interface. this information can be used to readjust the tuner frequency in order to reduce the analog filtering degradation on the sig- nal and thus improves the bit error rate. this information is also provided automatically to the dds in order to recover the frequency with complete accuracy before receive filtering. differential demodulation for qpsk a differential demodulation can be used in strongly dis- torted environment in the case of differentially encoded qpsk demodulation. this mode provides a stronger robustness against phase noise but reduces the perfor- mance of the receiver by 3 db, as shown in theory. i 2 c register qamsel must be configured to set this mode. phase and additive noise estimation phase noise and additive noise estimations are performed. this information can be used to select the best carrier loop bandwidth giving the best trade-off between phase noise and additive noise. the phase noise can come from the tuner and/or the lnb in mmds application. this feature can also be used to remotely monitor the various problems encountered by an stb or cable modem at the user installation. symbol detection and dvb/davic demapping the output is fed to the symbol threshold detector, then to the differential decoder and finally to the dvb or davic de- mapper, which produces the recovered bit stream sent to the forward error correction (fec). frame synchronization the first function performed by the fec is the frame syn- chronization. the bit stream is decomposed into packets of 204 bytes at the output, starting with a frame synchroniza- tion word. de-interleaving the packets are then de-interleaved. two depths can be selected for the interleaver: 12 (dvb/davic) and 17. the depth 17 increases the robustness of the system against impulse noise but assumes the signal has been interleaved with the same value as the modulator. reed-solomon decoder the de-interleaved output is sent to the reed-solomon (rs) input, which performs a correction of a maximum of eight errors (bytes) per packet. the rs also provides other information regarding the uncorrected packets and the position of the corrected bytes in the packet, if there are any. spectrum descrambler after rs decoding, the packets are descrambled for energy dispersal removal. pid filtering a program identifier (pid) filtering can be performed on the mpeg2 transport stream (ts) before feeding the packets to the output. three pids can be selected at the same time. this block outputs an enable signal on the packet stream that goes to the component interfaced with the qam demodulator. this provides an interesting feature for on- board pc implementations, where either data or video and audio are processed directly by the pc processor. a mask is provided for one of the pids, offering a filter on the over- all mpeg-ts packet header. note that one of the pids can be selected, so that a special enable output can be used to filter out all mpeg-ts pack- ets containing mac messages (for in-band return channel implementations of the dvb-rc specification). this stream contains all the control information for the return channel, and is required by other components used for the return channel.
AT76C651 7 interrupt request (irq) an interrupt request can be generated by the AT76C651 device when configurable events occur. this is controlled by the i 2 c registers irqmask and outputcfg. mpeg2-ts output interface the output of the fec is made up of mpeg2 transport stream (ts) packets. the output can be either parallel or serial on dataout. the data is present on either edge or low state of the datavalid pin in output mode. in serial output mode dataout (7) to dataout (1) are individu- ally valid, with each bit output in serial mode (see ? timing waveforms ? on page 35). oscillator and phase locked loop the fully digital clock and carrier recovery eliminates the need to implement external vcos and vcxos and thus reduces the total function cost. only a simple crystal oscil- lator is needed by the chip to perform all the demodulation functions with variable symbol rate. two configurations are possible: 1. a crystal can be connected to the xtal_i and xtal_o pins of the chip with frequency: values may depend on crystal characteristics. see figure 3, where r = 12 kohms and c = 20 pf. figure 3. 2. a crystal oscillator (xo) can be connected directly to the xoclk input pin, with frequency: in case of a crystal, the oscmode pin is connected to gnd. in case of an xo, it must be connected to v dd . the crystal must be first order, serial resonance and have a load capacitance of 10 pf. the internal oscillator of the chip provides a direct, jitter- free clock used to sample the input signal of external adc. this clock is available on the output pin adclk. the internal reference clock of the chip is generated by using an internal pll and its frequency is given by: the frequency f ref is the maximum output bit rate sup- ported by the device and must be less than 80 mhz (see ? symbol rate ? on page 13). the value n is configured by the pllctrl2, pllctrl1 and pllctrl0 input pins, as shown in table 2. note: other cases for test only. the value n = 2 allows to input directly the reference clock at frequency f ref (bypass the pll). the pll pin lftpll must be connected to an rc filter as shown in figure 4. values of resistance and capacitors should be r = 25 ? , c = 100 nf, and c2 = 20 nf. figure 4. rc filter connection to pll input of device a separate tunclk output pin provides a fraction of the crystal frequency given by: which can be used as a reference for the tuner oscillator or any other reference frequency on the board. the value p is configured by the i 2 c register, outputcfg (page 23). 25 mhz f xtal 30 mhz ? AT76C651 f xtal 80 mhz n = 2100 n = 4000 n = 5001 n = 6010 n = 7011 f ref n 2 -- - f xtal = with n 24567 ,,,, = lftpll r cc2 f tunclk 1 p -- - f xtal = with p 248 ,, =
AT76C651 8 jtag a jtag controller compatible with ieee std. 1149.1 is pro- vided in the device. the pin trst must be connected to a pull-down on the board in order to have it connected to gnd during functional operation of the chip. the jtag pro- vides a boundary scan chain on the pinout of the chip. the following instructions are available: bypass: the chip remains in functional mode and a single bypass register is connected between tdi and tdo. the bit code of this instruction is 11. sample/preload: the chip remains in functional mode and the boundary-scan register is connected between tdi and tdo. the bit code of this instruction is 01. extest:the chip is in external boundary-test mode and the boundary-scan register is connected between tdi and tdo. the bit code of this instruction is 00. idcode: the chip is in functional mode and the device identification register is connected between tdi and tdo. the bit code of this instruction is 10. the device identification register is 32 bits long and con- tains the value 0x00280b8f. special i/o description special i/os that are not described elsewhere in this speci- fication are described in this section. oscmode: when set to 1, a crystal oscillator is used. when set to 0, a crystal is used. test: three test pins are available on the chip for testing. 1. testmode: input test pin, connected to gnd 2. phasym: output test pin, not connected 3. ensym: output test pin, not connected ref2clk: clock output test pin, not connected i 2 c control the chip is controlled entirely via an i 2 c interface. the chip address can be modified by connecting the i2caddr pins to gnd or v dd3 to select the two lsbs of the address. the chip address is: i 2 c write mode registers can be written using a standard i 2 c bus with clock scl and data sda as described by ?the i 2 c-bus and how to use it?, philips semiconductors (april 1995). the protocol used to write into i 2 c registers is described by the frame shown below. s = start a = acknowledge bit p = stop ? data 1 is written at register address data 2 is written at register address + 1 ... data n is written at register address + (n - 1) it is therefore possible to configure several successive reg- isters with a single i 2 c frame (from first start to stop). 00011addi2c(1)addi2c(0) s chip address 0 (write) a register address a data 1 a ... data n ap to chip from chip
AT76C651 9 i 2 c read mode register values can be read from the chip by transmitting the following frames on the i 2 c bus. data x1 is read from register address data x2 is read from register address + 1 ... data xn is read from register address + (n - 1) it is therefore possible to read from several successive reg- isters with a single i 2 c frame (from first start to stop). note that multiple byte registers must be read msb/low address first. all lsbs of the complete data are memorized only at the time when msbs are read and do not change during readings of lsbs. switch for tuner i 2 c bus in order to avoid phase noise created by the i 2 c bus on the tuner, an active bi-directional switch provides a separate i 2 c bus for tuner configuration. for this purpose, the i 2 c bus to the tuner must be con- nected to the AT76C651 ti2cscl and ti2csda pins (see figure 1). the i 2 c register called tuni2cadd (see i 2 c registers table) must be configured with the i 2 c address of the tuner. the switch between the normal i 2 c bus and the tuner i 2 c bus can be enabled or disabled using the lsb of tuni2cadd. when disabled, ti2cscl/ti2csda lines are isolated from i2cscl/si2cda. when enabled, the switch copies i2csda to/from ti2csda when data is transmitted to/from the tuner. the switch should be enabled by the microcontroller only when the tuner is being configured. figure 5. i 2 c connection between AT76C651, tuner and microcontroller s chip address 0 (write) a register address a s chip address 1 (read) a data x1 a s chip address 1 (read) a data x2 a ... s chip address 1 (read) a data xn a or a p tuner scl sda ti2cscl ti2csda scl sda i2cscl i2csda microcontroller AT76C651
AT76C651 10 automatic configuration in order to configure the chip, the following actions are required: hard reset of chip configure registers symrate (symbol rate), qamsel (qam modulation type) and bbfreq (if frequency) write value 0x01 into setautocfg in order to automatically configure all other registers optionally modify some register values, if required write value 0x01 into restart in order to restart the chip with the new values the automatic configuration of all registers as a function of the qam modulation, symbol rate and if frequency offers a very simple use of the chip with a basic software driver.
AT76C651 11 table 3. i 2 c registers list address r/w name & function meaning general 0x00 to 0x02 w/r symrate symbol rate 0x03 w/r qamsel qam selection (and mapping type, dvb and others) 0x04 - 05 w/r bbfreq if input frequency 0x06 w setautocfg sets automatic configuration of all parameters (see note) 0x07 w restart restart chip without modifying configuration parameters 0x08* w/r outputcfg select mpeg2 or other internal signals for test output 0x09* w/r masklock1 mask for lock 1 signal output 0x0a* w/r masklock2 mask for lock 2 signal output 0x0b* w/r irqmask events mask for interrupt request generation 0x0c* w/r tuni2cadd tuner i 2 c address for use of specific tuner i 2 c bus 0x0e - 0x0f r chipid chip id and version baseband conversion and agc1 0x13* w/r agc1nmin minimum value authorized for agc value 0x14* w/r agc1nmax maximum value authorized for agc value 0x15* w/r bbcfg general configuration of baseband block 0x17* w/r cstpwm constant value for pwm output 0x19 r bbtopcnt a/d saturation rate over 16384 successive samples timing recovery 0x23 - 0x24* w/r timloopcfg configuration of initial loop parameters 0x29 r timloopmonit variable loop bandwidth value carrier recovery 0x31* w/r caralphaacq alpha parameter of loop bandwidth during acquisition phase of carrier 0x32* w/r carbetaacq beta parameter of loop bandwidth during acquisition phase of carrier 0x33* w/r caralphatrack alpha parameter of loop bandwidth during tracking phase of carrier 0x34* w/r carbetatrack beta parameter of loop bandwidth during tracking phase of carrier 0x39 - 0x3b r carconst constellation points after carrier recovery agc2 0x42* w/r agc2cfg agc2 configuration 0x43 - 0x44* w/r agc2init agc2 initial value equalizer 0x51* w/r equcfg equalizer configuration 0x52* w/r equcentral central tap configuration 0x53* w/r equtaptord coefficient to monitor
AT76C651 12 note: all parameters identified by * are automatically configured when writing 0x01 into setautocfg register. 0x54 - 0x55 r equtapreal real part of selected tap 0x56 - 0x57 r equtapimag imaginary part of selected tap fec 0x60* w/r feciqinv i/q invert mode 0x61* w/r fecflen frame length 0x62* w/r fecfsw frame synchronization word 0x63* w/r fecdilvilen number of branches in interleaver 0x64* w/r fecdilvmlen memory step size of interleaver 0x65* w/r fecdinh fec inhibitions configuration pid filtering 0x70 - 0x71* w/r pid1 first pid filter 0x72 - 0x73* w/r pid2 second pid filter 0x74 - 0x76* w/r pid3 third mpeg-ts header filter 0x77 - 0x79* w/r pidmsk3 mask for third mpeg-ts header filter general monitoring 0x80 r lock lock status of agc1, agc2, timing, carrier, equalizer, fec 0x81 - 0x83 r ber1 bit error rate estimate 0x84 r ber2 bit error rate estimate based on frame synchronization word 0x85 r nperr number of uncorrectable frames 0x86 - 0x88 r timfreqoff symbol rate frequency offset with respect to symrate 0x89 - 0x8a r ddsfreqoffset frequency offset recovered by dds 0x8b - 0x8c r carfreqoffset residual frequency offset (normalized to symbol rate) 0x8d - 0x8e r phasenoise phase noise estimation 0x8f - 0x90 r additivenoise additive noise estimation 0x91 r agc1level agc1 current value (external) 0x92 - 0x93 r agc2level agc2 current value (internal) table 3. i 2 c registers list (continued) address r/w name & function meaning
AT76C651 13 performance specification modulation supports qpsk and 16, 32, 64, 128, 256, 512, 1024 qam. roll-off factor greater than 0.11. symbol rate up to f ref /8 (9.36m baud for f ref = 75 mhz, f xtal = 30 mhz) with if or baseband input, 32-taps equalizer. up to f xtal /(2(1 + )) (13m baud for f ref = 30 mhz, = 0.15) with if input, 16-taps equalizer. up to f ref /4 (18.75m baud for f ref = 75 mhz, f xtal = 30 mhz) with baseband input, 16-taps equalizer. note however, that the standard mpeg2-ts frame recov- ery and forward error correction part of the chip can only be used when bitrate f ref . it is possible to use the constella- tion mode in the opposite case in order to use the demodulation part of the chip only and receive the symbols at the output. (see outputcfg register i 2 c to configure this operating mode.) bit error rate figures in the section ? bit error rate measurements (uncoded) ? on page 20 indicate bit error rate (ber) as a function of carrier-to-noise ratio (c/n) for different qam modulations schemes. theoretical curves are given to indi- cate how much degradation is observed with the real performance of the chip. table 5 indicates the degradation from theory (implementa- tion margin) for uncoded qam at ber = 10 -4 . echo cancellation table 6 indicates the additional degradation between use of a theoretical equalizer and the real chip equalizer, for uncoded qam at ber = 10 -4 , when the channel has the transfer response shown in figure 6. table 4. bandwidth f xtal = f adclk dds freq n (ctrlpll) f ref dsym_max 6 mhz 25 mhz 2x25-44 = 6 mhz 4 50 mhz 50/8 = 6.25 mbd 8 mhz 28.9 mhz 36-28.9 = 7 mhz 4 57.8 mhz 57.8/8 = 7.225 mbd table 5. modulation scheme c/n degradation at ber = 10 -4 qpsk 0.1 db qam-16 0.2 db qam-32 0.2 db qam-64 0.2 db qam-128 0.3 db qam-256 0.4 db qam-512 0.5 db qam-1024 0.7 db table 6. modulation scheme c/n degradation at ber = 10 -4 qpsk 0.3 db qam-16 0.3 db qam-32 0.3 db qam-64 0.3 db qam-128 0.3 db qam-256 0.3 db qam-512 0.3 db qam-1024 0.4 db
AT76C651 14 figure 6. received spectrum used to measure degradation with echoes phase noise tolerance table 7 indicates the additional degradation when a phase noise of -80 dbc at 10 khz is present after the tuner, for uncoded qam at ber = 10 -4 . am hum tolerance input amplitude variation of 20% peak-to-peak can be sup- ported by the demodulation at frequencies 100 - 120 hz. locking time 5 to 10 ms, when no echoes are present 20 ms typical when echoes are present (see figure 6) carrier offset up to 12% of the symbol rate: 1 mhz at 8m baud. timing offset up to 4000 ppm of the symbol rate ( 30 khz at 8m baud). table 7. modulation scheme c/n degradation at ber = 10 -4 qpsk 0.1 db qam-16 0.1 db qam-32 0.1 db qam-64 0.1 db qam-128 0.1 db qam-256 0.1 db qam-512 0.3 db qam-1024 0.9 db
AT76C651 15 electrical characteristics table 8. electrical specification ? recommended operating conditions symbol parameter conditions min typ max unit v dd5 i2cvdd, i 2 c dc supply voltage i 2 c and agc1 i/os v dd3 55.5v v dd3 vdd, dc supply voltage core and standard i/os 3.0 3.3 3.6 v v ss gnd, i2cgnd 0v temp operating free air temperature range commercial 0 +70 c table 9. absolute maximum ratings ? before damage symbol parameter conditions min max unit v dd3 dc supply voltage core and standard i/os -0.3 4.6 v v i dc input voltage, 3.3v i/os -0.3 v dd3 + 0.3, 4.6 max v dc input voltage, 5v i/os -0.3 v dd5 + 0.3, 5.5 max v v o dc output voltage, 3.3v i/os -0.3 v dd3 + 0.3, 4.6 max v dc output voltage, 5v i/os -0.3 v dd5 + 0.3, 5.5 max v temp operating free air temperature range commercial 0 +70 c table 10. dc characteristics for pins using vdd3 ? cmos technology symbol parameter conditions vdd min max unit temp temperature 0 +70 c v il low-level input voltage guaranteed input low voltage 3.0 to 3.6 -0.3 0.3 x v dd3 v v ih high-level input voltage guaranteed input high voltage 3.0 to 3.6 +0.7 x v dd3 v dd3 + 0.1v v v ol low-level output voltage i ol = 0.3ma 3.0 v ss + 0.1v v v oh high-level output voltage i oh = 0.3ma 3.0 v dd3 - 0.1 v c i input capacitance v dd3 6 (typ) pf table 11. dc characteristics for pins using vdd5 symbol parameter conditions min max unit v il low-level input voltage guaranteed input low voltage -0.3 +0.8 v v ih high-level input voltage guaranteed input high voltage 2.0 v dd5 + 0.3 v v ol low-level output voltage i ol = 2ma 0.4 v v oh high-level output voltage i oh = 2ma v dd5 - 0.4 v
AT76C651 16 schematic diagrams figure 7. standard use of AT76C651 in set top box front end figure 8. simplified use of AT76C651 when no analog tv demodulation required tuner dvb vid snd dvb/pal/ntsc downconverter analog AT76C651 qam demodulator mpeg2 xtal agc adc tuner dvb AT76C651 qam demodulator mpeg2 xtal agc adc
AT76C651 17 packaging information 100-lead tqfp package. commercial temperatures: 0 to 70 c. thermal resistance of the package: 40 c/w. figure 9. package outline note: the i/os located between pins i2cvdd (14) and i2cgnd (22) must use v dd5 voltage. all other i/os must use v dd3 voltage. vdd i 2 c a d d r 1 i2caddr0 gnd gnd ifqbb3 ifqbb2 ifqbb1 ifqbb0 vdd qbb1 qbb0 phasym ensym vdd vdd reset* oscmode adclk ref2clk testadc vdd gnd lftpll pllctrl2 pllctrl0 pllctrl1 nc i2cgnd i2cscl i2csda ti2cscl ti2csda i2cvdd tunclk a g c c s t p w m gnd ifibb5 ifibb3 ifibb2 gnd ifibb1 ifibb0 gnd ifibb4 vdd tms tck gnd tdo trst gnd flagpid0 flagpid1 vdd dataout0 dataout1 dataout2 gnd dataout4 dataout5 dataout6 dataout7 vdd irq dataout3 gnd 1 2 6 51 76 v d d v d d g n d v d d v d d xtal_i xtal_o xoclk gnd lock1 vdd corfail corbyte frmvalid frmstart datavalid vdd gnd smplphase lock2 gnd gnd vdd 12 3 8 63 88 testmode tdi gnd vdd vdd nc nc nc nc
AT76C651 18 figure 10. 100-lead tqfp package table 12. lead count dimensions (mm) pin count d/e bsc d1/e1 bsc bb1 e bsc ccc ddd min nom max min nom max 100 16.0 14.0 0.17 0.22 0.27 0.17 0.2 0.23 0.50 0.10 0.06 pin 1 aaa bbb c c 1 ddd 2 3 s l1 r1 r2 0.25 c cc 1
AT76C651 19 table 13. common dimensions (mm) symbol min nom max c0.09 0.2 c1 0.09 0.16 l 0.45 0.6 0.75 l1 1.00 ref r2 0.08 0.2 r1 0.08 s0.2 q0 3.5 7 10 211 12 13 311 12 13 a1.6 a1 0.05 0.15 a2 1.35 1.4 1.45 tolerances of form and position aaa 0.2 bbb 0.2
AT76C651 20 bit error rate measurements (uncoded) figure 11. qam-64 figure 12. qam-256
AT76C651 21 figure 13. qam-1024
AT76C651 22 configuration and monitoring registers description the AT76C651 device is controlled by an i 2 c interface. most internal registers are in read/write mode (configura- tion registers). however, monitoring registers are in read- only mode. note also that two special registers are write- only: setautocfg and restart. in most applications, very few of these registers need to be configured since the setautocfg can be used. some registers are not described in this document. they are used internally and should not be written with a different value after setau- tocfg; otherwise performance degradation may result. this means that no other address than the ones specified in this document should be used in i 2 c write mode. also, reserved bits in a register should always be written with the value 0. general registers symrate: 0x00 to 0x02 (read/write) transmission symbol rate, f symbol , registers give the initial symbol rate of the timing recovery algorithm. a maximum offset of 4000 ppm between the actual symbol rate and this value can be tolerated by the device. the internally com- pensated frequency offset can be monitored in the register timfreqoff. the symbol rate is given as a fraction of the refclk fre- quency. the value must be given with a mantissa (21 bits) and an exponent (3 bits). to compute these values, the following equations can be used: with example: for a 30 mhz crystal and pllctrl = 5, f ref = 75 mhz a symbol rate of 5m bauds gives: exponent = 6 (0x6) mantissa = 1 118 481(0 x 11 11 11) so the register value is 0x 88 88 8e. a symbol rate of 6.875m bauds gives: exponent = 6 (0x6) mantissa = 1 537 911(0 x 17 77 77) so the register value is 0 x bb bb be (default value). qamsel: 0x03 (read/write) specifies the used modulation scheme. this register indi- cates the number of qam levels and other parameters such as the used mapping type (dvb or others), whether coherent demodulation or differential demodulation is used for qpsk, and whether intermediate frequency (if) or baseband (bb) input is used. iforbb: 0 for if input signal, 1 for bb input signal demtyp: 0 for coherent demodulation, 1 for differential demodulation (in qpsk only) maptyp: 00 for dvb mapping, 10 for davic mapping, other values reserved qamtyp: number of bits to specify a qam symbol. example: 2 for qpsk, 4 for qam-16, 5 for qam-32, 6 for qam-64, 7 for qam-128, 8 for qam-256, 9 for qam-512, 10 for qam-1024 (0, 1, 3, and greater or equal to 11 are reserved values.) mantissa (20:13) 0x00 mantissa (12:5) 0x01 mantissa (4:0) exponent (2:0) 0x02 b7 b6 b5 b4 b3 b2 b1 b0 f ref f xtal 2 ------------- - ?? ?? pllctrl = pllctrl 24 , 5 , 67 , , = exponent 10 floor 2 log f symbol f ref ---------------- - ? ? ? ? ? ? ? ? + = mantissa f symbol f ref ---------------- - ?? ?? 2 30 onent exp ? = ifor bb dem typ maptyp qamtyp 0x03 b7 b6 b5 b4 b3 b2 b1 b0
AT76C651 23 bbfreq: 0x04 to 0x05 (read/write) intermediate frequency to baseband-down conversion fre- quency registers indicate the initial frequency used to down-convert the signal from if to bb. the value is between 0 and f adclk /2, where f adclk is the sampling fre- quency of the adc. a maximum offset between the actual if and this value of 12% of the symbol rate can be tolerated by this device. this offset can be monitored in the dds- freqoffset and carfreqoffset registers. the frequency is computed by: example: for a 30 mhz crystal and a signal at if frequency f if = 6 mhz, bbfreq1 = 51 (0x33) and bbfreq0 = 51 (0x33). note also that subsampling can be used with this device. this means that the if can be greater than the sampling frequency of the signal. for example, it is possible to have a sampling frequency f adclk = 30 mhz, and the if at f if = 36 mhz. in that case, an image of the spectrum after sam- pling is present at f if2 = 36 - 30 = 6 mhz, thus the content of bbfreq should correspond to f if2 . setautocfg: 0x06 (write-only) the automatic configuration address, when written with the value 0x01, automatically updates all registers of the device except for symrate, qamsel and bbfreq, which remain the same. all values are derived from these non-modified registers, thus offering a very straightforward configuration of the entire device without necessarily understanding the meaning of all other parameters. how- ever, if necessary, it is possible to modify some register values after having used setautocfg. in order to optimize the performance of the ic, the following values must be written into the ic after setautocfg has been performed. restart: 0x07 (write-only) this address, when written with the value 0x01, restarts the device without modifying the content of i 2 c registers. all recovery loops (agc, timing, carrier) and the equalizer restart from their initial value. this should always be done after a setautocfg or any reconfiguration of i 2 c registers. outputcfg: 0x08 (read/write) the data output configuration register configures the output format on pins dataout7 to dataout0 of the device. tundiv specifies the frequency of the clock signal output on tunclk pin. the frequency of this clock is given by: so p can take the values: 2, 4 or 8. when tundiv = 3, there is no output on tunclk pin in order to reduce power consumption if not needed. outputmode can take the following binary values: 000: mpeg2-ts parallel (dvb common interface) 001: mpeg2-ts serial 010: constellation before decision 011: i output after agc1 and baseband conversion 100: i output after timing recovery 101: i output after a/d sampling irqpol configures the polarity of the irq output pin: 0: irq is in high impedance or has value 0 when interruptions occur (see irqmask register). 1: irq is in high impedance or has value 1 when interruptions occur (see irqmask register). example: 0x0 configures mpeg2-ts parallel output with irq going low when interruptions occur. the default value after set- autocfg is 0x30. bbfreq1 (15:8) 0x04 bbfreq0 (7:0) 0x05 b7 b6 b5 b4 b3 b2 b1 b0 f if bbfreq 1 256 bbfreq 0 + 65536 ---------------------------------------------------------------- - f adclk = register value 0x10 0x06 0x11 0x10 0x15 0x28 0x20 0x09 0x24 0x90 reserved tundiv irq pol 0x08 b7 b6 b5 b4 b3 b2 b1 b0 outputmode f tunclk 1 p -- - f xtal = with p 2 tundiv 1 + =
AT76C651 24 masklock1: 0x09 (read/write) this register specifies the lock signals that must be moni- tored on the lock1 output pin. if all internal lock signals configured by this mask go high, then lock1 goes high. fec: mask on forward error correction lock signal car: mask on carrier recovery loop lock signal equ: mask on equalizer lock signal tim: mask on symbol rate recovery lock signal agc2: mask on digital agc lock signal agc1: mask on analog agc lock signal adc: mask on analog agc level lock signal pll: mask on phase locked loop (pll) lock signal setautocfg configures masklock1 at value 0x80, corresponding to the fec lock signal only. masklock2: 0x0a (read/write) this register specifies the lock signals that must be moni- tored on the lock2 output pin. if all internal lock signals configured by this mask go high, then lock2 goes high. setautocfg configures masklock2 at value 0x70, corresponding to the lock signals of the carrier recovery, the equalizer and the timing recovery, which is the full demodulator. irqmask: 0x0b (read/write) mask for irq output pin. this register specifies the mask on events that should activate the irq pin. irq goes to the value specified by irqpol (see outputcfg configuration) when any of the events specified by the mask described below occur and goes back to high impedance when any i 2 c register is written by the microcontroller. unlck1: irq when lock1 signal goes from 1 to 0 lck1: irq when lock1 signal goes from 0 to 1 unlck2: irq when lock2 signal goes from 1 to 0 lck2: irq when lock2 signal goes from 0 to 1 sat: irq when signal input loss (agc saturation) frmlst: irq when frame was lost time_win: periodic generation of irq 00: irq not activated by time delay 01: irq activated every 2048 frames 10: irq activated every 16384 frames 11: irq activated every 10 8 bits setautocfg configures the mask on unlock1. tuni2cadd: 0x0c (read/write) i 2 c address of tuner when connected to i 2 c bus of device (pins ti2cscl and ti2csda). for more details on the tuner i 2 c switch principle, see ? i 2 c read mode ? on page 9. en enables the switch when set to 1. note: en should be set to 1 when tuner is configured. then en must be set back to 0. chipid: 0x0e to 0x0f (read) gives information about chip number and version. value is 0x6510 (AT76C651, version a). baseband conversion and agc1 agc1nmin: 0x13 (read/write) specifies the minimum (or maximum) amplification value of agc1 given by the pwm output pin, which is between 0 and 255 when bbcfg(4) = 0 or bbcfg(4) = 1. for more details about the bbcfg register, see the description below. this value can be used to saturate amplification in case of non-linearities of the amplifier at extreme values. example: 0x00 (for maximum amplifying range) fec car equ tim 0x09 b7 b6 b5 b4 b3 b2 b1 b0 agc 2 agc 1 adc pll fec car equ tim 0x0a b7 b6 b5 b4 b3 b2 b1 b0 agc 2 agc 1 adc pll unlck 1 lck 1 unlck 2 lck 2 0x0a b7 b6 b5 b4 b3 b2 b1 b0 frm lst sat time_win tuner i 2 c address 0x0c b7 b6 b5 b4 b3 b2 b1 b0 en 0x0e 0x0f b7 b6 b5 b4 b3 b2 b1 b0 01100101 00010000 agc1nmin 0x13 b7 b6 b5 b4 b3 b2 b1 b0
AT76C651 25 agc1nmax: 0x14 (read/write) specifies the maximum (or minimum) amplification value of agc1 given by the pwm output pin, which is between 0 and 255 when bbcfg(4) = 0 or bbcfg(4) = 1. for more details about the bbcfg register, see the description below. this value can be used to saturate amplification in case of non-linearities of the amplifier at extreme values. example: 0xff (for maximum amplifying range) bbcfg: 0x15 (read/write) general control of if to bb conversion. this register con- trols several parameters of the agc1 control loop, internal dc-offset compensation and agc output format. res: reserved (must be configured with 0 when writing register) dccon: dc-offset control. if set to 0, the internal dc- offset compensation is on. if set to 1, the internal dc- offset control is off. the dc-offset should be on when the input signal is in bb. sgnam: sign of the amplifier control command (see figure 14) figure 14. sgnam configuration for amplifier gain control adccon: specifies whether adclevel must be automatically adapted in the presence of adjacent channels or if it must keep its initial value defined by register agc1initadc. automatic adaptation is configured by 0; no adaptation is configured by 1. pwmcon: specifies output format for agc and cstpwm pins. if set to 0, the agc control is output in pwm format on agc pin, and a completely configurable value (see cstpwm register) is output in pwm format on cstpwm pin. if set to 1, the agc control is output in differential format on agc and cstpwm pins. in this case, differential integration must be performed in the analog domain. in case of a pwm output, the agc pin should be con- nected to an rc filter with a cut-off frequency of maximum 1 khz. example: r = 1.5 k ? , c = 1 f note: the pwm output pin can be power supplied by 5v through the i2cvdd power supply. this assumes i 2 c bus functions at 5v. cstpwm: 0x17 (read/write) specifies a configurable value between 0 and 255, which is given in pwm format on cstpwm pin in case bbcfg(1) = 0. the cstpwm pin should be connected to an rc filter with a cut-off frequency of maximum 1 khz. example: r = 1.5 k ? , c = 1 f this voltage output can be used to control any other device on the board, like other amplifier gain control, variable capacitor, etc. note: this pin can output 5v since it is power-supplied by the i2cvdd power supply (this assumes i 2 c bus functions at 5v). example: cstpwm = 0x7f (2.5v in case 5v is connected to i2cvdd) bbtopcnt: 0x19 (read) this monitoring register indicates the number of a/d satu- rations over 16384 successive samples. this register can take values between 0 and 255. 255 indicates that more than 255 a/d saturations have occurred during the last 16384 samples. when the demodulator is working properly, this value should indicate 0x00. agc1nmax 0x14 b7 b6 b5 b4 b3 b2 b1 b0 res res dc con sgn am 0x15 b7 b6 b5 b4 b3 b2 b1 b0 adc con res pwm con res amplifier gain control voltage sgnam = 0 sgnam = 1 cstpwm 0x17 b7 b6 b5 b4 b3 b2 b1 b0 bbtopcnt 0x19 b7 b6 b5 b4 b3 b2 b1 b0
AT76C651 26 timing recovery timloopcfg: 0x23 to 0x24 (read/write) these two registers configure the loop bandwidth of the timing recovery loop. example: 0x7f for register 0x23 and 0x9 for register 0x24 the three parameters blmax_mexp, blmin_mexp and bltrack_mexp are 4-bit unsigned numbers that must follow the conditions: 7 blmax_mexp blmin_mexp 15 7 bltrack_mexp 15 they are related to the bandwidth blmax, blmin and bltrack by the formula: blmax is the maximal and initial bandwidth value used with a robust (gardner type) comparator. blmin is the minimal bandwidth value that can be taken by the loop bandwidth with the same comparator. when blmax > blmin, the loop can automatically decrease when the lock indicator is posi- tive or increase when this signal detects that the timing recovery system is out of lock. this variable bandwidth allows fast convergence, large timing frequency lock-in range in initial acquisitio1 n phase and low timing jitter when the system is locked. bltrack is the fixed value of the bandwidth used with deci- sion base comparator. typical values corresponding to the example above are: blmax = 2 -7 ? blmax_mexp = 7 blmin = 2 -15 ? blmin_mexp = 15 bltrack = 2 -9 ? bltrack_mexp = 9 timloopmonit: 0x29 (read) this monitoring register indicates the value of the automat- ically variable loop bandwidth. bandwidth bl, which is given by formula: bl_mexp is an unsigned value, taking values from blmax_mexp to blmin_mexp (see timloopcfg). when timing is well recovered, bl is equal to blmin. carrier recovery caralphaacq/carbetaacq: 0x31/0x32 (read/write) these two registers select the carrier loop bandwidth dur- ing acquisition phase. through those 2 bytes one can control the bandwidth and the damping factor ( ) of the loop filter. table 14 depicts some typical values for caralphaacq and carbetaacq. in automatic configuration, these parameters correspond to bl f symbol = 0.03 and = 1.0. caralphatrack/carbetatrack: 0x33/0x34 (read/write) these two registers select the carrier loop bandwidth dur- ing tracking phase (after acquisition). the same table as given for (0x31/0x32) configures these parameters. the switch between tracking phase and acquisition phase takes place when agc2, equalizer and carrier are locked. in automatic configuration, these parameters correspond to bl f symbol = 0.03 and = 4.0. blmax_mexp 0x23 bltrack_mexp 0x24 b7 b6 b5 b4 b3 b2 b1 b0 reserved blmin_mexp blx 2 -blx_mexp = bl_mexp 0x29 b7 b6 b5 b4 b3 b2 b1 b0 reserved bl 2 -bl_mexp = table 14. b l f symbol caralphaacq carbetaacq 0.005 0.7 0xae 0x9c 0.005 1.0 0x98 0x98 0.005 2.0 0x9a 0xbc 0.005 4.0 0x9a 0xdd 0.010 0.7 0x9e 0x7c 0.010 1.0 0x88 0x78 0.010 2.0 0x8a 0x9c 0.010 4.0 0x8a 0xbd 0.030 0.7 0x7a 0x4d 0.030 1.0 0x7c 0x49 0.030 2.0 0x7e 0x6d 0.030 4.0 0x7f 0x8e 0x31 0x32 b7 b6 b5 b4 b3 b2 b1 b0 carbetaacq caralphaacq caralphatrack 0x33 0x34 b7 b6 b5 b4 b3 b2 b1 b0 carbetatrack
AT76C651 27 carconst: 0x39/0x3a/0x3b (read) the constellation points after gain adjustment, timing recovery, equalization and carrier recovery can be col- lected without breaking down the demodulation and the channel decoding. the two components (i, q), with 12-bit precision, are collected in three bytes: byte 1 (0x39): 8 msb of i byte 2 (0x3a): 8 msb of q byte 3 (0x3b): the 4 msb of byte 3 are equal to the 4 lsb of i and the 4 lsb of byte 3 are equal to the 4 lsb of q. byte 1 should be collected first. when the address of this byte is detected by the AT76C651, then a constellation point (i: 12 bits, q: 12 bits) is memorized and only the 8 msbs of i are sent as data on the i 2 c bus. byte 2 and byte 3 can be collected later; their content does not change unless byte 1 is collected again. agc2 agc2cfg: 0x42 (read/write) two operating modes exist for agc2: boost mode and nor- mal mode. after a reset or a soft clear, the agc2 is in boost mode and unlocked. during this phase, equalizer and car- rier are inhibited. the switch from boost mode to normal mode happens when agc2 locks. the agc2 loop bandwidth can be controlled through loopbw2 during boost mode and by loopbw1 during normal mode. in both cases the loop bandwidth is proportional to loopbw. table 15 gives the value of agc2cfg for the different qam in automatic configuration. agc2init: 0x43 and 0x44 (read/write) these registers configure the initial agc2 gain. agc2init is coded in a floating format with a mantissa coded with 11 unsigned bits and an exponent coded with 5 signed bits, defined as follows: exponent must be in the range -6 to 13, and mantissa takes its value in the range 1024 to 2047. equalizer equcfg: 0x51 (read/write) this register controls the equalizer operating mode. inh: when set to 1, this parameter inhibits the equalizer; all equalizer taps are set to 0 except central tap, which is equal to 1 (in complex format). in standard configuration it is set to 0. fre: when set to 1 it freezes the equalizer taps adaptation. the equalizer behaves as a complex fir (finite impulse response). in standard configuration it is set to 0. len: the equalizer has 32 taps when this parameter is set to 1 and only 16 taps when set to 0. the first mode can be selected only if the ratio between f ref and f symbol is higher or equal to 8(f ref /f symbol 8). in standard configuration it is set to 1. i (11:4) 0x39 q (11:4) 0x3a i (3:0) q (3:0) 0x3b b7 b6 b5 b4 b3 b2 b1 b0 res 0x42 b7 b6 b5 b4 b3 b2 b1 b0 loopbw2 loopbw1 table 15. qam agc2cfg qpsk 0x34 qam-16 0x35 qam-32 0x35 qam-64 0x34 qam-128 0x33 qam-256 0x32 qam-512 0x31 qam-1024 0x30 0x43 mantissa (2:0) 0x44 b7 b6 b5 b4 b3 b2 b1 b0 exponent (4:0) mantissa (10:3) exponent floor 2 log agc 2 gain ()) ( = mantissa floor agc 2 gain 2 exponent ? 1024 () = inh fre len structure 0x51 b7 b6 b5 b4 b3 b2 b1 b0 step
AT76C651 28 structure: two equalizer structures are implemented in the AT76C651: le (linear equalizer) and dfe (decision feedback equalizer). when b5 = 1, only le structure can be selected. in dfe mode two substructures, depending on the position of the central tap, can be configured. table 16 shows the different possibilities. step: this parameter controls the step used to adapt the equalizer taps. the higher the step, the higher the adaptation step. equcentral: 0x52 (read/write) central tap position: equcentral (4:0) gives the position of the equalizer central tap. this position should be set between 0 and 31 when equcfg(5)=1 and between 0 and 15 when equcfg(5)=0. in standard configuration this parameter is set to 7. adapt: the central tap adaptation mode can be selected between the configurations shown in table 17: in standard configuration it is set to 11. equtaprord: 0x53 (read/write) this parameter selects the position of the equalizer tap that we want to collect (see ? equtapreal: 0x54/0x55 (read) and equtapimag: 0x56/0x57 (read) ? ). the number of taps that can be read depends of the equalizer length (see ? equcfg: 0x51 (read/write) ? ). equtapreal: 0x54/0x55 (read) and equtapimag: 0x56/0x57 (read) after selecting the equalizer tap to read (see ? equtap- rord: 0x53 (read/write) ? ), the real part and the imaginary part of the tap are collected in four bytes. the first byte to read must be 0x54. when the AT76C651 detects this address, it memorizes the equalizer tap value (4 bytes) and sends the 8 msbs of the real part as read data. the three other bytes can be collected later. the value of the tap is equal to: table 16. b4b3 structure 00 le 10 le 01 dfe with central tap position between 0 and 7 11 dfe with central tap position between 8 and 15 res adapt 0x52 b7 b6 b5 b4 b3 b2 b1 b0 central tap position table 17. b6b5 real part imag part 00 adapted adapted 01 adapted fixed to 0 10 fixed to 1 adapted 11 fixed to 1 fixed to 0 reserved 0x53 b7 b6 b5 b4 b3 b2 b1 b0 equalizer tap position 0x54 msb 0x55 lsb b7 b6 b5 b4 b3 b2 b1 b0 equtapreal (7:0) equtapreal (15:8) 0x56 msb 0x57 lsb equtapimag (7:0) equtapimag (15:8) real ( j imag ) + signed () equtapreal () () j signed equtapimag () () + 16384 ------------------------------------------------------------------------------------------------------------------------------- -------------------- =
AT76C651 29 fec feciqinv: 0x60 (read/write) configuration of i and q inversion. this register indicates if the i and q channel must be swapped before de-mapping. an automatic mode is also provided. iqinv is a read-only single bit that indicates if i and q channel are swapped (in manual mode it is equal to b0). iqinvcmd is composed of two bits (read/write): the msb (b1) controls the use of the automatic mode (= 0) or the manual mode (= 1); the lsb (b0) is used in manual mode to swap i and q channel. note: the automatic mode uses the frame structure to choose the right configuration. if the frame is not recovered, iqinv can change at any time. fecflen: 0x61 (read/write) frame length configuration. the size of frame can be configured. flen is an 8-bit value that gives the length of the frame. this value should be higher than 50 to guarantee a correct func- tioning of the fec decoder. example: for dvb mpeg2-ts, the frame length is 204. this is the default value. note: the reed-solomon parity length is always 16 bytes and is counted in the frame length. fecfsw: 0x62 (read/write) frame synchronization word configuration. fsw is an 8-bit value that gives the normal value of the first byte in a frame. in dvb, the first byte of the frame is period- ically bit-to-bit inverted to synchronize the descrambler. example: for dvb mpeg2-ts, the frame synchronization word is 0x47, which is also the default value. fecdilvilen: 0x63 (read/write) number of branches in the de-interleaver. dilvilen is a 5-bit value that gives the number of branches in the de-interleaver. see fecdilvmlen below for constraints. example: for standard dvb-c mpeg2-ts, dilvilen should be set to 12 (default value). fecdilvmlen: 0x64 (read/write) memory step size of the de-interleaver. dilvmlen is a 5-bit value that gives the memory step size of the de-interleaver (described in the dvb standard). the first branch has (dilvilen-1) x dilvmlen memory byte. the second branch has (dilvilen-2) x dilvmlen memory bytes. the third branch has (dilvilen-3) x dilvmlen memory bytes. ... the dilvilenth branch has 0 memory bytes. the first byte of a frame is always routed to the first branch in the de-interleaver. to allow a correct synchronization, the following formula must be respected by the user: the internal memory is limited to 2k bytes of ram: example: for dvb mpeg2-ts, dilvmlen must be set to 17 (default value). however, it can sometimes be advantageous to use fecdi- vilen = 17 with fecdilvmlen = 12 (keeping fecflen = 204) to get a better impulsive errors spreading. reserved 0x60 b7 b6 b5 b4 b3 b2 b1 b0 iqinvcmd iqinv flen 0x61 b7 b6 b5 b4 b3 b2 b1 b0 fsw 0x62 b7 b6 b5 b4 b3 b2 b1 b0 dilvilen 0x63 b7 b6 b5 b4 b3 b2 b1 b0 reserved dilvmlen 0x64 b7 b6 b5 b4 b3 b2 b1 b0 reserved fecdilvilen fecdilvmlen flen = flen fecdilvilen 1 ? () 2 ---------------------------------------------------- - fecdilvilen + 2048 <
AT76C651 30 fecinh: 0x65 (read/write) inhibition of selected parts of the forward error correction blocks. fecinh is a 7-bit value. each bit set to 1 indicates that the selected function is inhibited. the hardware block is then in a transparent mode. example: for dvb mpeg2-ts, fecinh should be set to 0x00 (default value) but to execute an external bit error rate measure, b3, b5 and b6 should probably be set to 1 (fecinh = 0x68). for non-dvb applications, with fecinh = 0x7e, it is possi- ble to get data after qam de-mapping and differential decoder in serial mode or in parallel mode (bytes are not aligned). pid filtering pid1: 0x70 to 0x71 (read/write) first mpeg pid to filter. this function can be disabled. pid1 is a 14-bit value that gives the first mpeg pid to flag. this function is provided to enable the use of a simple soft- ware mpeg de-multiplexer. bit 5 of the register 0x70 is an enable. when this function is enabled and if the 13-bit pid of an incoming frame matches pid1, the flagpid0 pin takes the value 1 and the flagpid1 pin takes the value 0. this filter has a higher priority than pid2 and pid3. the default value is 0x0000 so the function is disabled. pid2: 0x72 to 0x73 (read/write) second mpeg pid to filter. this function can be disabled. pid2 is a 14-bit value that gives the second mpeg pid to flag. this function is provided to enable the use of simple software mpeg de-multiplexer. bit 5 of the register 0x72 is an enable. when this function is enabled, if the 13-bit pid of an incoming frame matches pid2 and if pid1 flag is not set, the flagpid1 pin takes the value 1 and the flagpid0 pin takes the value 0. this filter has a higher pri- ority than pid3, but lower than pid1. the default value is 0x0000, so the function is disabled. pid3: 0x74 to 0x76 (read/write) and pidmsk3: 0x77to 0x79 (read/write) third pid to filter. this filter has a 24-bit length with a mask of the same length. pid3 is a 24-bit value that gives the third pid (the 2nd, 3rd and 4th bytes of frame) to flag. this function is provided to enable the use of a simple software mpeg de-multiplexer. a 24-bit mask is also provided by registers 0x77 to 0x79. the mpeg header bits are only checked with pid3 if the corresponding bits in pidmsk3 are set to 1. if pidmsk3 is set to 0x000000, the function is disabled. if pid1 or pid2 get a match for a particular frame, pid3 fil- ter is not performed for this frame. when pid3 gets a match, both pins flagpid0 and flagpid1 are set to 1. this filter has a lower priority than pid1 and pid2. the default value is 0x000000 for pid3 and pidmsk3. this function is disabled. table 18. fecinh bits functions inhibited comments b0: diff differential decoder useful for non-coherent demodulation b1: frm frame synchronization prevent bit skipping if frames not needed b2: dilv de-interleaver cannot be synchronized without frames b3: rs reed-solomon decoder error detection without correction b4: scrm scrambler need inverted fecfsw for synchronization b5: force 1st byte forced to fecfsw cannot be used without frame recovery b6: beind bit error indicator (msb of 2nd byte) enable external bit error rate measure 0x65 b7 b6 b5 b4 b3 b2 b1 b0 res beind force scrm rs dilv frm diff reserved enpid1 0x70 0x71 b7 b6 b5 b4 b3 b2 b1 b0 pid1 (7:0) pid1 (12:8) reserved enpid2 0x72 0x73 b7 b6 b5 b4 b3 b2 b1 b0 pid2 (7:0) pid2 (12:8) pid3 (23:16) 0x74 b7 b6 b5 b4 b3 b2 b1 b0 pid3 (15:8) 0x75 pid3 (7:0) 0x76 pidmsk3 (23:16) 0x77 pidmsk3 (15:8) 0x78 pidmsk3 (7:0) 0x79
AT76C651 31 general monitoring lock: 0x80 (read) this monitoring register indicates the lock status of agc1, agc2, timing recovery, carrier recovery, equalizer, fec and the pll. fec: lock signal for fec car: lock signal for carrier recovery equ: lock signal for equalizer tim: lock signal for timing recovery agc2: lock signal for digital agc (agc2) agc1: lock signal for analog agc (agc1) adc: lock signal for agc1 power reference value adaptation pll: lock signal for pll ber1: 0x81 to 0x83 (read) this monitoring register indicates the bit error rate estimate over the last 10 8 bits. this register indicates the number of corrected bit errors in the last 10 8 bits, but does not take into account the frames that are not correctable, i.e., the frames in which more than eight errors have occurred (this value can be monitored in register nperr). ber2: 0x84 (read) this monitoring register indicates another bit error rate esti- mate based on a counter of false frame synchronization words. this register is meaningful when the bit error rate is greater than 10 -3 . the bit error rate is given by: nperr: 0x85 (read) this monitoring register indicates the number of uncorrect- able frames in the last 10 8 bits. the value is saturated at 255 if more than 255 uncorrectable frames have occurred. timfreqoff: 0x86 to 0x88 (read) this monitoring register indicates the value of the recov- ered symbol rate offset with respect to the configured symbol rate (see ? symbol rate ? on page 13). timfreqoff is a positive integer value directly read in the loop filter memory. this value is scaled by a gain factor k l inside the chip and is added to the configured symbol rate. the result is used to control the timing of the numerically controlled oscillator, and is the recovered symbol rate. therefore, it is possible to compute the real recovered sym- bol rate offset ? t (in hz) with the following formula: the scaling factor k l is internally defined as the approxima- tion of the configured symbol rate given in the following formula: where exponent and mantissa are the configured symbol rate exponent plus 10 and symbol rate mantissa (see ? symbol rate ? on page 13). fec equ car tim 0x80 b7 b6 b5 b4 b3 b2 b1 b0 agc 2 agc 1 adc pll reserved 0x81 b7 b6 b5 b4 b3 b2 b1 b0 ber1(20:16) 0x82 ber1(15:8) 0x83 ber1(7:0) ber2 4096 ------------ - ber2 0x84 b7 b6 b5 b4 b3 b2 b1 b0 nperr 0x85 b7 b6 b5 b4 b3 b2 b1 b0 0x86 0x87 b7 b6 b5 b4 b3 b2 b1 b0 timfreqoff (15:8) timfreqoff (23:16) 0x88 timfreqoff (7:0) ? t timfreqoff k l 2 29 -------------------------------------- = k l floor mantissa ( 2 16 ? ) 2 4 ? 2 exponent-10 =
AT76C651 32 ddsfreqoffset: 0x89 to 0x8a (read) this monitoring register indicates the frequency offset recovered by the dds (at if to bb down conversion). this value, added to the frequency entered in register bbfreq, gives the corrected if frequency of the input signal. this value is a fraction of the crystal frequency f xtal . the offset frequency is given by: carfreqoffset: 0x8b to 0x8c (read) this monitoring register indicates the frequency offset recovered by the carrier. the collected value is normalized to symbol rate. address 0x8b (msbs) must be read from the device first in order to ensure the correctness of the content of 0x8c (lsbs). the offset frequency is given by: the total frequency offset recovered is given by: phasenoise: 0x8d to 0x8e (read) the residual phase noise (after carrier recovery) is esti- mated. the collected information contains the phase noise due to oscillators and also the phase noise due to the addi- tive noise integrated by the carrier loop filter. below is an explanation of how to compute the total residual phase noise and how to extract the phase noise due to additive noise. in the following formula: ? denotes the residual phase noise and 2 ? the mean of ? squared. the parameter a depends on the qam format and is given table 19: the phase noise portion due to the integration of the addi- tive noise by the loop filter is given by: the parameter depends of the qam format and is given by the table below. 2 ? denotes the mean square of the additive noise description (see ? additivenoise: 0x8f to 0x90 (read) ? on page 33), and b l the selected carrier loop bandwidth for tracking phase. the residual phase noise due to oscillator impairments is then equal to: using 2 ? osc , the configured loop bandwidth, the symbol rate and an assumption about the tuner phase noise shap- ing, an estimate of the phase noise at a given frequency offset can be obtained. 0x89 0x8a b7 b6 b5 b4 b3 b2 b1 b0 ddsfreqoffset (7:0) ddsfreqoffset (15:8) f ddsfreqoffset ddsfreqoffset f xtal 2 20 ------------------------------------------------------- = 0x8b 0x8c b7 b6 b5 b4 b3 b2 b1 b0 carfreqoffset (7:0) carfreqoffset (15:8) f carfreqoffset signed carfreqoffset () f symbol 2 17 -------------------------------------------------------------------------------- - = ? ff ddsfreqoffset f carfreqoffset + = 0x8d 0x8e b7 b6 b5 b4 b3 b2 b1 b0 phasenoise (7:0) phasenoise (15:8) table 19. qam a (db) qpsk -45.15 qam-16 -54.69 qam-32 -54.69 qam-64 -62.05 qam-128 -62.05 qam-256 -68.67 qam-512 -68.67 qam-1024 -74.98 table 20. qam qpsk 2.53e-2 qam-16 to qam-1024 2.83e-2 2 ? db () adb () 10 10 phasenoise () log () + = 2 ? n b l 2 n = 2 ? osc 2 ? 2 ? n ? =
AT76C651 33 the example below shows how to make this computation when the tuner phase noise level decreases by 20 db each time frequency offset is multiplied by 10. the result is given by the following formula: phasenoise spd is the phase noise spectral density at fre- quency offset ( ? f) given in hz. is a constant that depends on the carrier loop filter. see table 21. note: the phase noise information is not relevant if the demod- ulator is not locked. additivenoise: 0x8f to 0x90 (read) an estimate of the additive noise level is implemented in the AT76C651. it can be used to compute the s/n (signal- to-noise) ratio. byte 0x8f should be collected first in order to ensure the correctness of 0x90. when the demodulator is not locked, this information is not relevant. the following formula shows how to compute the s/n (db) or the eb/n (db) for each qam format. n denotes the additive noise and 2 n the mean of n square. s/n (db) = 10 x log10(a) - 2 n (db) eb/n (db) = 10 x log10(b) - 2 n (db) table 22 gives the values of a and b for each qam. agc1level: 0x91 (read) this monitoring register indicates the present level of agc1, which is output in pwm format to agc output pin. the value is between agc1nmin and agc1nmax. agc1level indicates the control voltage value (v) applied at the input of the external amplifier, through the rc filter, connected to the agc pin. it is given by: where i2cvdd is the power supply connected to pin i2cvdd (5v or 3.3v). table 21. b l 0.005 0.7 1460 0.005 1.0 1250 0.005 2.0 1030 0.005 4.0 980 0.010 0.7 720 0.010 1.0 600 0.010 2.0 510 0.010 4.0 480 0.030 0.7 225 0.030 1.0 180 0.030 2.0 160 0.030 4.0 150 phasenoise spd 2 ? osc f symbol hz () ? f () 2 ? -------------------------------------------------------- - dbc () hz () ? = additivnoise (15:8) 0x8f additivnoise 0 (7:0) 0x90 b7 b6 b5 b4 b3 b2 b1 b0 table 22. qam a b qpsk 2 1 qam-16 10 10/4 qam-32 20 20/5 qam-64 42 42/6 qam-128 82 82/7 qam-256 170 170/8 qam-512 330 330/9 qam-1024 682 682/10 2 n db () 10 10 log additivenoise 2 16 ----------------------------------- - ?? ?? = agc1level 0x91 b7 b6 b5 b4 b3 b2 b1 b0 v agc 1 level 255 ------------------------- - i 2 cvdd =
AT76C651 34 agc2level: 0x92 to 0x93 (read) these registers allow the user to monitor the current value of agc2 gain. agc2level is coded in a floating format with a mantissa coded with 11 unsigned bits and an exponent coded with 5 signed bits, and is defined as follows: exponent takes its value in the range -6 to 13, and man- tissa takes its value in the range 1024 to 2047. 0x92 mantissa (2:0) 0x93 b7 b6 b5 b4 b3 b2 b1 b0 exponent (4:0) mantissa (10:3) exponent floor 2 log agc 2 gain ()) ( = mantissa floor agc 2 gain 2 exponent ? 1024 () =
AT76C651 35 timing waveforms output interface figure 15. parallel mpeg2-ts output figure 16. serial output mode datavalid dataout[7..0] frmstart frmvalid corbyte corfail 16 bytes 188 bytes fsw 2/f ref 4/f ref 2/f ref datavalid dataout (7) dataout (6) dataout (5) ... dataout (1) dataout (0) frmstart b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4
AT76C651 36 input interface the input pin samplephase must be connected to gnd or vdd, as indicated in the following table. see figure 17 for the definition of t pa d and t adclk . figure 17. external a/d converter input table 23. samplephase t pa d typ 0t pa d t adclk /4 or t pad 3t adclk /4 1 t adclk /4 t pa d 3t adclk /4 adclk a/d output t adclk t pad
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